Tortall yasm → 1.2.0

Originally posted on Trac by sirus@haxsys.net
Original Trac Ticket

  Description

The following instructions according to the Intel ISA should assemble but do not:

lfs RAX, tword [RBX] ;( error : invalid size for operand 1)
lgs RAX, tword [RBX] ;( error : invalid size for operand 1)
lss RAX, tword [RBX] ;( error : invalid size for operand 1)

movsx RAX, BH ;( error : cannot use A/B/C/DH with instruction needing REX)
movzx RAX, BH ;( error : cannot use A/B/C/DH with instruction needing REX)

Trac Attachments

h3. Trac Comments
comment:1

              Changed 11 hours ago by peter@tortall.net

For lfs/lgs/lss, you're right, they should indeed support 64-bit destinations and currently don't.  I'll get this fixed.

"movsx/movzx reg64, ah/bh/ch/dh" is not legal.  There's an explicit exception for this case in the Intel ISA manual: "In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH."  The REX prefix is needed to activate the 64-bit operand size (for reg64) so it's not legal to combine a reg64 destination with a ah/bh/ch/dh source.  The technical reason for this is when REX is used, it remaps the bit patterns used for ah/bh/ch/dh to instead mean sil,dil,bpl,spl (the low 8 bits of rsi,rdi,rbp,rsp respectively).

comment:2

              Changed 11 hours ago by sirus@haxsys.net

Ah you are correct there. My mistake about the movsx/movzx.